HyperTransport System Architecture
Editorial Reviews
Book Description
The MindShare Architecture Series The MindShare Architecture book series currently includes the books listed below. Rather than duplicating common information in each book, the series uses the building-block approach. Generally speaking, ISA System Architecture is the core book upon which the others build. In a sense, it is a PC-compatibility book. The entire book series is published by Addison-Wesley. Books about Processor Architecture: 80486 System Architecture, Third Edition , 0-201-40994-1 Pentium Processor System Architecture Second Edition , 0-201-40992-5 Pentium Pro and Pentium II System Architecture, Second Edition , 0-201-30973-4 Power PC System Architecture , 0-201-40990-9 Books About Bus Architecture: PCI System Architecture, Fourth Edition , 0-201-30974-2 PCI-X System Architecture , 0-201-72682-3 EISA System Architecture , 0-201-40995-X--Out-of-print Firewire System Architecture, Second Edition: IEEE 1394a , 0-201-48535-4 ISA System Architecture, Third Edition , 0-201-40996-8 Universal Serial Bus System Architecture , 0-201-46137-4 HyperTransport System Architecture , 0-321-16845-3 Books About Network Architecture: Network Architecture Infiniband Network Architecture , 0-321-11765-4 Books About Other Architectures: PCMCIA System Architecture, Second Edition: 16-Bit PC Cards , 0-201-40991-7 CardBus System Architecture , 0-201-40997-6 Plug and Play System Architecture , 0-201-41013-3 Protected Mode Software Architecture , 0-201-55447-X AGP System Architecture , 0-201-37964-3 Cautionary Note The reader should keep in mind that MindShare's book series often details rapidly evolving technologies. That being the case, it should be recognized that the book is a "snapshot" of the state of the technology at the time the book was completed. We make every attempt to produce our books on a timely basis, but the next revision of the specification is not introduced in time to make necessary changes. At the time of this writing, the HyperTransport I/O Link Specification Revision 1.04 is released. The 1.04 revision of the specification does not deal with the networking extensions but much of the work on the HyperTransport 1.05 and 1.1 revisions has been done by the HyperTransport Technical Working Group, and quite a bit of preliminary information on this important addition to the protocol has been released. Some of the more important additions to these specifications are summarized in this book. Please check the MindShare Web site ([a href="http://www.mindshare.com" target="_new">www.mindshare.com ) for supplemental information, updates, and errata. Intended Audience This book is intended for use by hardware and software design and support personnel. The tutorial approach taken may also make it useful to technical personnel not directly involved design, verification, and other support functions. Prerequisite Knowledge It is recommended that the reader has a reasonable background in PC architecture, including experience or knowledge of an I/O bus and related protocol. The MindShare publication entitled ISA System Architecture focuses on various aspects of PCI architecture and provides the necessary background. Topics and Organization Topics covered in this book and the flow of the book are as follows: Part 1: Overview of HyperTransport Chapter 1: Introduction to HyperTransport Chapter 2: HT Architectural Overview Part 2: HyperTransport Core Topics Chapter 3: Signal Groups Chapter 4: Packet Protocol Chapter 5: Flow Control Chapter 6: I/O Ordering Chapter 7: Transaction Examples Chapter 8: HT Interrupts Chapter 9: System Management Chapter 10: Error Detection and Handling Chapter 11: Routing Packets Chapter 12: Reset and Initialization Chapter 13: Device Configuration Chapter 14: Electrical Chapter 15: Clocking Part 3: HyperTransport Optional Topics Chapter 16: HyperTransport Bridges Chapter 17: Double-Hosted Chains Chapter 18: HT Power Management Chapter 19: Networking Extensions Overview Part 4: HyperTransport Legacy Support Chapter 20: I/O Compatibility Chapter 21: Address Remapping Chapter 22: x86 CPU Compatibility Appendix A: Glossary of Terms Index Documentation Conventions This section defines the typographical convention used throughout this book. HyperTransport HyperTransport is a trademark of the HyperTransport Consortium. This book takes the liberty of abbreviating HyperTransport as "HT" to improve readability. Hexadecimal Notation All hex numbers are followed by a lower case "h." For example: 89F2BD02h 0111h Binary Notation All binary numbers are followed by a lower case "b." For example: 1000 1001 1111 0010b 01b Decimal Notation Numbers without any suffix are decimal. When required for clarity, decimal numbers are followed by a lower case "d." Examples: 9 15 512d Byte Terminology and Notation This book uses the following terminology regarding quantities of data: 8-bits = 1 byte 16-bits = 2 bytes, Word 32-bits = 4 bytes, Double Word, Dword, or DW 64-bits = 8 bytes, Quad Word, Qword, or QW Bits Versus Bytes Notation This book represents bit with lower case "b" and bytes with an upper case "B."For example: Megabits/second = Mb/s Megabytes/second = MB/s Bit Fields and Groups of Signals Groups of signals or bits are represented with the high-order bits first followed by the low-order bits and enclosed by brackets. For example: 7:0 Addr39:0 CAD15:0 Active Signal States Signals that are active low are followed by #, as in RESET#. Active high signalshave no suffix following the signal, as in PWROK. Visit Our Web Site Our web site lists all of our courses and the delivery options available for each course: Self-paced DVDs and CDs Live web-delivered classes Live on-site classes All of our books are listed and can be ordered in bound or e-book versions www.mindshare.com We Want Your Feedback MindShare values your comments and suggestions. Contact us at: Phone: (719) 487-1417 or within the U.S. (800) 633-1440 Fax: (719) 487-1434 E-mail: don@mindshare.com or jay@mindshare.com For information on MindShare seminars, DVDs, and books, check our Web siteor contact nancy@mindshare.com Mailing Address: MindShare, Inc. 4285 Slash Pine Drive Colorado Springs, CO 80908 0321168453P02032003
From the Back Cover
HyperTransport™ (HT) technology promises to revolutionize connectivity for computers, servers, embedded systems, and networking and tele-communications equipment. It is a high-speed, low latency, point-to-point, packetized link that enables chips to transfer data at peak rates of up to 12.8 Gigabytes per second, far greater than existing bus technologies. Furthermore, HyperTransport improves reliability and reduces board design complexity. It is scalable and compatible with legacy PC buses, SNA, and PCI.
HyperTransport™ System Architecture provides a comprehensive, technical guide to HyperTransport technology. It opens with an overview of HT systems, highlighting the technology's fundamental principles, basic architecture, and its many advantages. The book goes on to detail all facets of HyperTransport systems, including the protocol, I/O, routing, configuration, and more. It also features important performance considerations and addresses critical compatibility issues.
Essential topics covered include:
A chapter is dedicated to transaction examples illustrating the practical application of HyperTransport technology.
A MindShare PC System Architecture Series book, HyperTransport™ System Architecture provides complete, authoritative, and detailed information necessary for developers, networking professionals, and anyone interested in implementing and deploying HT systems.
MindShare's PC System Architecture Series is a crisply written and comprehensive set of guides to the most important PC hardware standards. Books in the series are intended for use by hardware and software designers, programmers, and support personnel. Each title explains the architecture, features, and operations of systems built using one particular type of chip or hardware specification.
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